Output Capacitance Loss Measurement and Validation for Low-Voltage Silicon and GaN Devices in DC-DC Converter Applications
| dc.contributor.author | Soni, Abhinav | en |
| dc.contributor.committeechair | Lai, Jih S. | en |
| dc.contributor.committeemember | Li, Qiang | en |
| dc.contributor.committeemember | Dimarino, Christina Marie | en |
| dc.contributor.department | Electrical Engineering | en |
| dc.date.accessioned | 2023-07-15T08:00:33Z | en |
| dc.date.available | 2023-07-15T08:00:33Z | en |
| dc.date.issued | 2023-07-14 | en |
| dc.description.abstract | With the rise of soft-switched converter topologies which enable high-frequency power conversion, there has been a premise that these converter topologies can help achieve loss-less switching in a power device. However, this theory is not completely true as there even with soft-switching there is some degree of loss associated in the form of output capacitance-related hysteresis loss, channel turn-off loss, and loss during the dead-time period in these converter topologies. The soft-switching converters utilize the existence of the device's output capacitance (COSS), which is charged and discharged consecutively at each switching cycle, and a hysteresis loss exists due to the difference in charging and discharging output capacitance. In order fully utilize the potential of these novel soft-switching topologies, we need to investigate further into the origins of these losses or loss mechanisms, methods to measure or compute these losses, and then devise ways to optimize the loss for a given application. This work focuses on exploring methods to quantify this loss for different operating conditions like device current, switching frequency, dV/dT, etc. In this aspect, some methods have been studied and used to quantify this hysteresis loss for a variety of power devices like SI and GaN. It is reported that only channel turn-off losses exist in devices with ZVS transition, however, we found that the charging and discharging of COSS is not loss-free and thus it is important that we account for this loss in the design process. Finally, the loss data obtained from these tests are compared with each other for five different power devices to validate their applicability, and later these test results are used to get an optimized device selection criterion for the best possible efficiency and minimal losses for a ZVS application. | en |
| dc.description.abstractgeneral | To eliminate the switch-related losses, soft-switching or zero-voltage switching (ZVS) was introduced which provides a soft transition of voltage and current instead of a sharp transition like in hard-switched converters. Moreover, the output capacitance of the devices is charged/discharged to achieve soft switching, which also possesses a loss (hysteresis loss) due to repeated charging and discharging of output capacitance. Soft-switching converter topologies have gained quite a momentum for almost a decade, and it keeps on increasing in the distant future, to extract the maximum benefits from these topologies is to operate at high switching frequencies to minimize the size and volume of the converter. However, the hysteresis loss can severely impact the converter efficiency on even a few 100 kHz and MHz levels. This work focuses on exploring methods to measure hysteresis loss in output capacitance which has a major share in the overall switching loss. In this regard, some methods have been investigated that deal with the measurement of the output capacitance-related hysteresis loss and are implemented to get the hysteresis loss data for different power devices. Two test methods (calorimetric and non-linear resonance) are implemented on five different power devices (3 SI and 2 GaN) to get the energy loss in the output capacitance; these test results are used to explain the switching loss in an isolated boost resonance DC-DC converter, and a concept of ZVS figure of merit is used to obtain the optimized device. Moreover, a design example of a soft-switched converter is presented to highlight the impact of COSS hysteresis loss in the overall switching loss of primary side devices. | en |
| dc.description.degree | Master of Science | en |
| dc.format.medium | ETD | en |
| dc.identifier.other | vt_gsexam:37983 | en |
| dc.identifier.uri | http://hdl.handle.net/10919/115779 | en |
| dc.language.iso | en | en |
| dc.publisher | Virginia Tech | en |
| dc.rights | In Copyright | en |
| dc.rights.uri | http://rightsstatements.org/vocab/InC/1.0/ | en |
| dc.subject | COSS hysteresis loss | en |
| dc.subject | calorimetric test | en |
| dc.subject | non-linear resonance test | en |
| dc.subject | ZVS figure of merit | en |
| dc.title | Output Capacitance Loss Measurement and Validation for Low-Voltage Silicon and GaN Devices in DC-DC Converter Applications | en |
| dc.type | Thesis | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.grantor | Virginia Polytechnic Institute and State University | en |
| thesis.degree.level | masters | en |
| thesis.degree.name | Master of Science | en |
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