Development of a Low-Power SRAM Compiler

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dc.contributor.authorJagasivamani, Meenatchien
dc.contributor.committeechairHa, Dong Samen
dc.contributor.committeememberTront, Joseph G.en
dc.contributor.committeememberArmstrong, James R.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:44:57Zen
dc.date.adate2000-09-11en
dc.date.available2014-03-14T20:44:57Zen
dc.date.issued2000-09-01en
dc.date.rdate2001-09-11en
dc.date.sdate2000-09-08en
dc.description.abstractConsiderable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in the ASIC environment. The compiler generates an SRAM layout based on a given SRAM size, input by the user, with the option of choosing between fast vs. low-power SRAM. Array partitioning is used to partition the SRAM into blocks in order to reduce the total power consumption. Experimental results show that the low-power SRAM is capable of functioning at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz. In this report, we discuss the implementation of the SRAM compiler from the basic component to the top-level SKILL code functions, as well as simulation results and discussion.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-09082000-03290016en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-09082000-03290016/en
dc.identifier.urihttp://hdl.handle.net/10919/34963en
dc.publisherVirginia Techen
dc.relation.haspartthesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectSRAMen
dc.subjectcompileren
dc.subjectstaticen
dc.subjectgeneratoren
dc.subjectVLSIen
dc.subjectMemoryen
dc.subjectlow-poweren
dc.subjectRAMen
dc.titleDevelopment of a Low-Power SRAM Compileren
dc.typeThesisen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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