Design and Analysis of Four Architectures for FPGA-Based Cellular Computing

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dc.contributor.authorMorgan, Kenneth J.en
dc.contributor.committeechairArmstrong, James R.en
dc.contributor.committeememberJones, Mark T.en
dc.contributor.committeememberAthanas, Peter M.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:47:23Zen
dc.date.adate2004-11-09en
dc.date.available2014-03-14T20:47:23Zen
dc.date.issued2004-10-19en
dc.date.rdate2004-11-09en
dc.date.sdate2004-11-03en
dc.description.abstractThe computational abilities of today's parallel supercomputers are often quite impressive, but these machines can be impractical for some researchers due to prohibitive costs and limited availability. These researchers might be better served by a more personal solution such as a "hardware acceleration" peripheral for a PC. FPGAs are the ideal device for the task: their configurability allows a problem to be translated directly into hardware, and their reconfigurability allows the same chip to be reprogrammed for a different problem. Efficient FPGA computation of parallel problems calls for cellular computing, which uses an array of independent, locally connected processing elements, or cells, that compute a problem in parallel. The architecture of the computing cells determines the performance of the FPGA-based computer in terms of the cell density possible and the speedup over conventional single-processor computation. This thesis presents the design and performance results of four computing-cell architectures. MULTIPLE performs all operations in one cycle, which takes the least amount of time but requires the most chip area. BIT performs all operations bit-serially, which takes a long time but allows a large cell density. The two other architectures, SINGLE and BOOTH, lie within these two extremes of the area/time spectrum. The performance results show that MULTIPLE provides the greatest speedup over common calculation software, but its usefulness is limited by its small cell density. Thus, the best architecture for a particular problem depends on the number of computing cells required. The results also show that with further research, next-generation FPGAs can be expected to accelerate single-processor computations as much as 22,000 times.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-11032004-020914en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11032004-020914/en
dc.identifier.urihttp://hdl.handle.net/10919/35578en
dc.publisherVirginia Techen
dc.relation.haspartThesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectBooth Algorithmen
dc.subjectField programmable gate arraysen
dc.subjectSingle-Chip Computeren
dc.subjectCellular Computingen
dc.subjectBit-Serialen
dc.subjectParallel Computeren
dc.titleDesign and Analysis of Four Architectures for FPGA-Based Cellular Computingen
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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