On improving the performance of parallel fault simulation for synchronous sequential circuits

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dc.contributor.authorTiew, Chin-Yawen
dc.contributor.departmentElectrical Engineeringen
dc.date.accessioned2014-03-14T21:30:41Zen
dc.date.adate2009-03-04en
dc.date.available2014-03-14T21:30:41Zen
dc.date.issued1993en
dc.date.rdate2009-03-04en
dc.date.sdate2009-03-04en
dc.description.abstractIn this thesis, several heuristics that aim to improve the performance of parallel fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of faults simulated in parallel, the number of gate evaluations, and the CPU time. The three heuristics are critical path tracing, dynamic area reduction and a new heuristic called two level simulation. Critical path tracing and dynamic area reduction which have been previously proposed for combinational circuits are extended for synchronous sequential circuits in this thesis. The two level simulation that was investigated in this thesis is designed for sequential circuits. Experimental results show that critical path tracing is the most effective of the three heuristics. In addition to the three heuristics, new fault injection and fault ordering methods were suggested to improve the speed of an efficient fault simulator called HOPE. HOPE, which was developed at Virginia Tech is, an improved version of PROOFS. HOPE_NEW, which incorporates the two heuristics performs better than HOPE in the number of gate evaluations and the CPU time. HOPE_NEW is about 1.13 times faster than HOPE for the ISCAS89 benchmark circuits. For the largest circuit, the speedup is about 40 percent.en
dc.description.degreeMaster of Scienceen
dc.format.extentx, 88 leavesen
dc.format.mediumBTDen
dc.format.mimetypeapplication/pdfen
dc.identifier.otheretd-03042009-040323en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-03042009-040323/en
dc.identifier.urihttp://hdl.handle.net/10919/41387en
dc.language.isoenen
dc.publisherVirginia Techen
dc.relation.haspartLD5655.V855_1993.T538.pdfen
dc.relation.isformatofOCLC# 29040211en
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subject.lccLD5655.V855 1993.T538en
dc.subject.lcshElectric circuits, Parallelen
dc.subject.lcshElectric fault location -- Computer simulationen
dc.subject.lcshFault location (Engineering)en
dc.subject.lcshIntegrated circuits -- Very large scale integration -- Testingen
dc.titleOn improving the performance of parallel fault simulation for synchronous sequential circuitsen
dc.typeThesisen
dc.type.dcmitypeTexten
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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