Balancing Performance, Area, and Power in an On-Chip Network

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dc.contributor.authorGold, Brianen
dc.contributor.committeechairBaker, James M. Jr.en
dc.contributor.committeememberMichael S, Hsiaoen
dc.contributor.committeememberJones, Mark T.en
dc.contributor.departmentElectrical and Computer Engineeringen
dc.date.accessioned2014-03-14T20:41:52Zen
dc.date.adate2003-08-06en
dc.date.available2014-03-14T20:41:52Zen
dc.date.issued2003-07-23en
dc.date.rdate2003-08-06en
dc.date.sdate2003-07-24en
dc.description.abstractSeveral trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications. The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects. This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-07242003-134147en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-07242003-134147/en
dc.identifier.urihttp://hdl.handle.net/10919/34137en
dc.publisherVirginia Techen
dc.relation.haspartbtgthesis.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectareaen
dc.subjectvirtual channelsen
dc.subjectSCMPen
dc.subjectpoweren
dc.subjectnetworken
dc.subjectrouteren
dc.subjectcrossbar switchen
dc.subjectsingle chip computeren
dc.subjectmessage passingen
dc.subjectsystem on chipen
dc.titleBalancing Performance, Area, and Power in an On-Chip Networken
dc.typeThesisen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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