Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling

dc.contributor.authorGantz, Kevin Francisen
dc.contributor.committeechairAgah, Masouden
dc.contributor.committeememberHuxtable, Scott T.en
dc.contributor.committeememberRaman, Sanjayen
dc.contributor.committeememberNazhandali, Leylaen
dc.contributor.departmentMechanical Engineeringen
dc.date.accessioned2014-03-14T20:48:33Zen
dc.date.adate2008-01-17en
dc.date.available2014-03-14T20:48:33Zen
dc.date.issued2007-11-28en
dc.date.rdate2010-12-22en
dc.date.sdate2007-11-30en
dc.description.abstractA novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized.en
dc.description.degreeMaster of Scienceen
dc.identifier.otheretd-11302007-113409en
dc.identifier.sourceurlhttp://scholar.lib.vt.edu/theses/available/etd-11302007-113409/en
dc.identifier.urihttp://hdl.handle.net/10919/35863en
dc.publisherVirginia Techen
dc.relation.haspartKGantz_Thesis_Ch4.pdfen
dc.relation.haspartKGantz_Thesis_Ch5.pdfen
dc.relation.haspartKGantz_Thesis_Ch1_3.pdfen
dc.rightsIn Copyrighten
dc.rights.urihttp://rightsstatements.org/vocab/InC/1.0/en
dc.subjectnonlinear regressionen
dc.subjectisotropic etchingen
dc.subjectchip coolingen
dc.subjectCMOS compatibleen
dc.subjectRIE lagen
dc.subjectmicrofluidicsen
dc.titleFabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Coolingen
dc.typeThesisen
thesis.degree.disciplineMechanical Engineeringen
thesis.degree.grantorVirginia Polytechnic Institute and State Universityen
thesis.degree.levelmastersen
thesis.degree.nameMaster of Scienceen

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