Scholarly Works, Center for Power Electronics Systems

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https://hdl.handle.net/10919/111744

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A Highly Stabilized Current Source Topology with Slope Compensation for a High-Power Microwave Guiding Coil
Zhang, Dandi; Ding, Hongfa; He, Zhou; Zhou, Wentao; Zhang, Ziqi (MDPI, 2025-02-13)
For the waveguide coil in a High-Power Microwave (HPM) source, a strong repetitive Flat-top Pulsed Magnetic Field (FTPMF) is needed, which requires the power supply system to generate a high load current (3∼5 kA) with high stability (<1000 ppm) and a long pulse-width (15∼20 ms). To achieve this, this article proposes a novel topology which includes a capacitor bank as the main power supply to guarantee a long pulse-width, combined with an active current compensator to regulate the load current precisely. A PI control scheme with slope compensation is used to solve the current fluctuation caused by capacitor switching. The novel topology also features a fast rising and falling time, thus it is suitable for repetitive working applications. The parameters of the topology are calculated by analysis to guarantee the working condition of a 45 GHz HPM source, and the operating principle of this topology is verified through low-power-scale experiments.
Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching
Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-06)
The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage (VG) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under VG overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like VG overshoots with pulse width down to 20 ns and dVG/dt up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency (fSW). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of VG overshoot (VG(PK)) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max VG(PK) for 10-year gate lifetime is predicted under different fSW in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT’s converter applications and a new method for the device gate qualification.
1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier
Qin, Yuan; Xiao, Ming; Zhang, Ruizhe; Xie, Qingyun; Palacios, Tomás; Wang, Boyan; Ma, Yunwei; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Srijanto, Bernadeta R.; Zhang, Yuhao (IEEE, 2023-07)
This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plane junction electric field of 2.8 MV/cm. The device also shows low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 m ·cm2. Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.
10-kV Ga₂O₃ Charge-Balance Schottky Rectifier Operational at 200 ^◦C
Qin, Yuan; Xiao, Ming; Porter, Matthew; Ma, Yunwei; Spencer, Joseph; Du, Zhonghao; Jacobs, Alan G.; Sasaki, Kohei; Wang, Han; Tadjer, Marko; Zhang, Yuhao (IEEE, 2023-08)
This work demonstrates a lateral Ga2O3 Schottky barrier diode (SBD) with a breakdown voltage (BV) over 10 kV, the highest BV reported in Ga2O3 devices to date. The 10 kV SBD shows good thermal stability up to 200◦C, which is among the highest operational temperatures reported in multi-kilovolt Ga2O3 devices. The key device design for achieving such high BV is a reduced surface field (RESURF) structure based on the p-type nickel oxide (NiO), which balances the depletion charges in the n-Ga2O3 channel at high voltage. At BV, the chargebalanced Ga2O3 SBD shows an average lateral electric field (E-field) over 4.7 MV/cm at 25 ◦C and over 3.5 MV/cm at 200◦C, both of which exceed the critical E-field of GaN and SiC. The 10 kV SBD shows a specific on-resistance of 0.27 ·cm2 and a turn-on voltage of 1 V; at 200◦C, the former doubles and the latter reduces to 0.7 V. These results suggest the good potential of Ga2O3 devices for mediumand high-voltage, high-temperature power applications.
2 kV, 0.7 mΩ·cm² Vertical Ga₂O₃ Superjunction Schottky Rectifier with Dynamic Robustness
Qin, Yuan; Porter, Matthew; Xiao, Ming; Du, Zhonghao; Zhang, Hongming; Ma, Yunwei; Spencer, Joseph; Wang, Boyan; Song, Qihao; Sasaki, Kohei; Lin, Chia-Hung; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2023)
We report the first experimental demonstration of a vertical superjunction device in ultra-wide bandgap (UWBG) Ga2O3. The device features 1.8 μm wide, 2×1017 cm-3 doped n-Ga2O3 pillars wrapped by the charge-balanced p-type nickel oxide (NiO). The sidewall NiO is sputtered through a novel self-align process. Benefitted from the high doping in Ga2O3, the superjunction Schottky barrier diode (SJ-SBD) achieves a ultra-low specific on-resistance (RON,SP) of 0.7 mΩ·cm2 with a low turn-on voltage of 1 V and high breakdown voltage (BV) of 2000 V. The RON,SP~BV trade-off is among the best in all WBG and UWBG power SBDs. The device also shows good thermal stability with BV > 1.8 kV at 175 oC. In the unclamped inductive switching tests, the device shows a dynamic BV of 2.2 kV and no degradation under 1.7 kV repetitive switching, verifying the fast acceptor depletion in NiO under dynamic switching. Such high-temperature and switching robustness are reported for the first time in a heterogeneous superjunction. These results show the great potential of UWBG superjunction power devices.
Gate Robustness and Reliability of P-Gate GaN HEMT Evaluated by a Circuit Method
Wang, Bixuan; Zhang, Ruizhe; Song, Qihao; Wang, Hengyu; He, Quanbo; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2024-01)
The small gate overvoltage margin is a key reliability concern of the GaN Schottky-type p-gate high electron mobility transistor (GaN SP-HEMT). Current evaluation of gate reliability in GaN SP-HEMTs relies on either the DC bias stress or pulse I-V method, neither of which resembles the gate voltage (VGS) overshoot waveform in practical converters. This work develops a new circuit method to characterize the gate robustness and reliability in GaN SP-HEMTs, which features a resonance-like VGS ringing with pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. Using this method, the gate's single-pulse failure boundary, i.e., dynamic gate breakdown voltage (BVDYN), is first obtained under the hard switching (HSW) and drain-source grounded (DSG) conditions. The gate's switching lifetime is then tested under the repetitive VGS ringing, and the number of switching cycles to failure (SCTF#) is fitted by Weibull or Lognormal distributions. The SCTF# shows a power law relation with the VGS peak value and little dependence on the switching frequency. More interestingly, the gate's BVDYN and lifetime are both higher in HSW than those in DSG, as well as at higher temperatures. Such findings, as well as the gate degradation behaviors in a prolonged overvoltage stress test, can be explained by the time-dependent Schottky breakdown mechanism. The gate leakage current is found to be the major precursor of gate degradation. At 125 oC and 100 kHz, the VGS limits for a 10-year lifetime are projected to be ∼6 V and ∼10 V under the DSG and HSW conditions, respectively. These results provide a new qualification method and reveal new physical insights for gate reliability and robustness in p-gate GaN HEMTs.
Dynamic Gate Breakdown of p-Gate GaN HEMTs in Inductive Power Switching
Wang, Bixuan; Zhang, Ruizhe; Wang, Hengyu; He, Quanbo; Song, Qihao; Li, Qiang; Udrea, Florin; Zhang, Yuhao (IEEE, 2023-02)
We employ a new circuit method to characterize the gate dynamic breakdown voltage (BVdyn) of Schottky-type p-gate GaN HEMTs in power converters. Different from prior pulse I-V and DC stress tests, this method features a resonance-like gate ringing with the pulse width down to 20 ns and an inductive switching concurrently in the drain-source loop. At the increased pulse width, the gate BVdyn shows a decrease and then saturation at 21~22 V. Moreover, the gate BVdyn increases with temperature and is higher under the hard switching than that under the drain-source grounding condition. In the 400 V hard switching at 150 oC, the gate BVdyn reaches 27.5 V. Such impact of the drain switching locus and temperature on the gate BVdyn is not seen in Si and SiC power transistors tested in the same setup. These results are explained by a physics model that accounts for the electrostatics in the p-GaN gate stack in hard switching and at high temperatures. This work unveils new physics critical to the gate robustness of p-gate GaN HEMTs and manifest the necessity of the gate robustness evaluation in inductive switching conditions.
Dynamic R_ON Free 1.2 kV Vertical GaN JFET
Yang, Xin; Zhang, Ruizhe; Wang, Bixuan; Song, Qihao; Walker, Andy; Pidaparthi, Subhash; Drowley, Cliff; Zhang, Yuhao (IEEE, 2024)
Dynamic on-resistance (RON) or threshold voltage (VTH) instability caused by charge trapping is one of the most crucial reliability concerns of some GaN high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic RON and VTH stability of an industrial vertical GaN transistor-NexGen’s 1200V/70mΩ fin-channel JFET, fabricated on 100 mm bulk GaN substrates. A circuit setup is deployed for the in-situ measurement of the dynamic RON under steady-state switching. The longer-term stability of RON and VTH is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no RON or VTH shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices towards power electronics applications.
1 kV Self-Aligned Vertical GaN Superjunction Diode
Ma, Yunwei; Porter, Matthew; Qin, Yuan; Spencer, Joseph; Du, Zhonghao; Xiao, Ming; Wang, Yifan; Kravchenko, Ivan; Briggs, Dayrl P.; Hensley, Dale K.; Udrea, Florin; Tadjer, Marko; Wang, Han; Zhang, Yuhao (IEEE, 2024-01)
This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance ( RON) of 0.4 mΩ⋅ cm2, and a SJ drift-region resistance ( Rdr) of 0.13 mΩ⋅ cm2. The device also exhibits good thermal stability with B V retained over 1 kV and RON dropped to 0.3 mΩ⋅ cm2 at 125oC . The trade-off between B V and Rdr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.
Thermal management and packaging of wide and ultra-wide bandgap power devices: a review and perspective
Qin, Yuan; Albano, Benjamin; Spencer, Joseph; Lundh, James Spencer; Wang, Boyan; Buttay, Cyril; Tadjer, Marko; DiMarino, Christina; Zhang, Yuhao (IOP Publishing, 2023-03)
Power semiconductor devices are fundamental drivers for advances in power electronics, the technology for electric energy conversion. Power devices based on wide-bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors allow for a smaller chip size, lower loss and higher frequency compared with their silicon (Si) counterparts, thus enabling a higher system efficiency and smaller form factor. Amongst the challenges for the development and deployment of WBG and UWBG devices is the efficient dissipation of heat, an unavoidable by-product of the higher power density. To mitigate the performance limitations and reliability issues caused by self-heating, thermal management is required at both device and package levels. Packaging in particular is a crucial milestone for the development of any power device technology; WBG and UWBG devices have both reached this milestone recently. This paper provides a timely review of the thermal management of WBG and UWBG power devices with an emphasis on packaged devices. Additionally, emerging UWBG devices hold good promise for high-temperature applications due to their low intrinsic carrier density and increased dopant ionization at elevated temperatures. The fulfillment of this promise in system applications, in conjunction with overcoming the thermal limitations of some UWBG materials, requires new thermal management and packaging technologies. To this end, we provide perspectives on the relevant challenges, potential solutions and research opportunities, highlighting the pressing needs for device-package electrothermal co-design and high-temperature packages that can withstand the high electric fields expected in UWBG devices.
Artificial Neuronal Devices Based on Emerging Materials: Neuronal Dynamics and Applications
Liu, Hefei; Qin, Yuan; Chen, Hung-Yu; Wu, Jiangbin; Ma, Jiahui; Du, Zhonghao; Wang, Nan; Zou, Jingyi; Lin, Sen; Zhang, Xu; Zhang, Yuhao; Wang, Han (Wiley-V C H Verlag, 2023-03)
Artificial neuronal devices are critical building blocks of neuromorphic computing systems and currently the subject of intense research motivated by application needs from new computing technology and more realistic brain emulation. Researchers have proposed a range of device concepts that can mimic neuronal dynamics and functions. Although the switching physics and device structures of these artificial neurons are largely different, their behaviors can be described by several neuron models in a more unified manner. In this paper, the reports of artificial neuronal devices based on emerging volatile switching materials are reviewed from the perspective of the demonstrated neuron models, with a focus on the neuronal functions implemented in these devices and the exploitation of these functions for computational and sensing applications. Furthermore, the neuroscience inspirations and engineering methods to enrich the neuronal dynamics that remain to be implemented in artificial neuronal devices and networks toward realizing the full functionalities of biological neurons are discussed.
Power device breakdown mechanism and characterization: review and perspective
Zhang, Ruizhe; Zhang, Yuhao (IOP Publishing, 2023-04)
Breakdown voltage (BV) is arguably one of the most critical parameters for power devices. While avalanche breakdown is prevailing in silicon and silicon carbide devices, it is lacking in many wide bandgap (WBG) and ultra-wide bandgap (UWBG) devices, such as the gallium nitride high electron mobility transistor and existing UWBG devices, due to the deployment of junction-less device structures or the inherent material challenges of forming p-n junctions. This paper starts with a survey of avalanche and non-avalanche breakdown mechanisms in WBG and UWBG devices, followed by the distinction between the static and dynamic BV. Various BV characterization methods, including the static and pulse I-V sweep, unclamped and clamped inductive switching, as well as continuous overvoltage switching, are comparatively introduced. The device physics behind the time- and frequency-dependent BV as well as the enabling device structures for avalanche breakdown are also discussed. The paper concludes by identifying research gaps for understanding the breakdown of WBG and UWBG power devices.
Recent progress of Ga2O3 power technology: large-area devices, packaging and applications
Qin, Yuan; Wang, Zhengpeng; Sasaki, Kohei; Ye, Jiandong; Zhang, Yuhao (IOP Publishing, 2023-06)
Benefitted from progress on the large-diameter Ga2O3 wafers and Ga2O3 processing techniques, the Ga2O3 power device technology has witnessed fast advances toward power electronics applications. Recently, reports on large-area (ampere-class) Ga2O3 power devices have emerged globally, and the scope of these works have gone well beyond the bare-die device demonstration into the device packaging, circuit testing, and ruggedness evaluation. These results have placed Ga2O3 in a unique position as the only ultra-wide bandgap semiconductor reaching these indispensable milestones for power device development. This paper presents a timely review on the state-of-the-art of the ampere-class Ga2O3 power devices (current up to >100 A and voltage up to >2000 V), including their static electrical performance, switching characteristics, packaging and thermal management, and the overcurrent/overvoltage ruggedness and reliability. Exciting research opportunities and critical technological gaps are also discussed.
Vertical GaN diode BV maximization through rapid TCAD simulation and ML-enabled surrogate model
Lu, Albert; Marshall, Jordan; Wang, Yifan; Xiao, Ming; Zhang, Yuhao; Wong, Hiu Yung (Pergamon-Elsevier Science, 2022-12)
In this paper, two methodologies are used to speed up the maximization of the breakdown voltage (BV) of a vertical GaN diode that has a theoretical maximum BV of -2100 V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50 % more numbers of high BV (>1400 V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887 V (89 % of the ideal case) compared to -1100 V designed with human domain expertise.
Global Intergrid for Sustainable Energy Abundance
Boroyevich, Dushan; Cvetkovic, Igor; Dong, Dong (IEEE Power Electronics Society, 2022-06-04)
Invited Poster for Session on Brainstorming for Game-Changing Ideas.
Multidimensional device architectures for efficient power electronics
Zhang, Yuhao; Udrea, Florin; Wang, Han (Springer Nature, 2022-11-17)
Power semiconductor devices are key to delivering high-efficiency energy conversion in power electronics systems, which is critical in efforts to reduce energy loss, cut carbon dioxide emissions and create more sustainable technology. Although the use of wide or ultrawide-bandgap materials will be required to develop improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures—such as superjunction, multi-channel and multi-gate technologies—can enable advances in the speed, efficiency and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling and material figure of merits of the architectures, and identify key technological challenges that need to be addressed to realize the full potential of the approach.
Design of a 10 kV SiC MOSFET-based high-density, high-efficiency, modular medium-voltage power converter
Mocevic, Slavko; Yu, Jianghui; Fan, Boran; Sun, Keyao; Xu, Yue; Stewart, Joshua; Rong, Yu; Song, He; Mitrovic, Vladimir; Yan, Ning; Wang, Jun; Cvetkovic, Igor; Burgos, Rolando; Boroyevich, Dushan; DiMarino, Christina; Dong, Dong; Motwani, Jayesh Kumar; Zhang, Richard (IEEE, 2022-03)
Simultaneously imposed challenges of high-voltage insulation, high dv/dt, high-switching frequency, fast protection, and thermal management associated with the adoption of 10 kV SiC MOSFET, often pose nearly insurmountable barriers to potential users, undoubtedly hindering their penetration in medium-voltage (MV) power conversion. Key novel technologies such as enhanced gatedriver, auxiliary power supply network, PCB planar dc-bus, and high-density inductor are presented, enabling the SiC-based designs in modular MV converters, overcoming aforementioned challenges. However, purely substituting SiC design instead of Sibased ones in modular MV converters, would expectedly yield only limited gains. Therefore, to further elevate SiC-based designs, novel high-bandwidth control strategies such as switching-cycle control (SCC) and integrated capacitor-blocked transistor (ICBT), as well as high-performance/high-bandwidth communication network are developed. All these technologies combined, overcome barriers posed by state-of-the-art Si designs and unlock system level benefits such as very high power density, high-efficiency, fast dynamic response, unrestricted line frequency operation, and improved power quality, all demonstrated throughout this paper.
Role of power electronics in Grid 3.0
Zhang, Richard (IEEE, 2022-12)
A SiC-Based Liquid-Cooled Electric Vehicle Traction Inverter Operating at High Ambient Temperature
Zhang, Chi; Srdic, Srdjan; Lukic, Srdjan; Wang, Jun; Burgos, Rolando (China Power Supply Society, 2022-06-30)
This paper describes the design process of a high-power-density 100 kW (34 kW/L) traction inverter for electric vehicles, operating at an ambient temperature of 105 °C. A detailed thermal analysis is performed based on the thermal behavior of the switching devices, and the results are used to estimate the semiconductor device junction temperature and to determine the requirements of the cooling system to achieve the target power level. A high-temperature gate drive board aiming for reliable system operation in electric vehicles is developed. An overcurrent protection scheme based on parasitic inductance between the power source and the Kelvin source of the power module has been implemented. A dc-link decoupling snubber circuit is designed numerically based on a detailed forth-order high-frequency equivalent circuit of a double pulse test circuit. The approach to optimize the snubber circuit, not only for the voltage spike suppression but also for good thermal performance, is proposed. Finally, a hardware prototype with SiC power modules has been built and tested at 60 kW continuous power and 100 kW for 20 seconds at 105 °C ambient temperature and 65 °C inlet coolant temperature.
Superjunction Power Transistors With Interface Charges: A Case Study for GaN
Ma, Yunwei; Xiao, Ming; Zhang, Ruizhe; Wang, Han; Zhang, Yuhao (2019-12-13)
Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges for the first time. In our model, two approaches are proposed to compensate interface charges, by the modulation of the SJ doping or the SJ geometry. Based on our model, an analytical study is conducted for GaN SJ transistors, revealing the design windows and optimal values of doping concentration and pillar width as a function of interface charge density. Finally, TCAD simulation is performed for vertical GaN SJ transistors, which validated our analytical model. Our results show that, with optimal designs, interface charges would only induce small degradation in the performance of GaN SJ devices. However, with the increased interface charge density, the design windows for pillar width and doping concentration become increasingly narrow and the upper limit in the pillar width window reduces quickly. When the interface charge density exceeds similar to 3X10(12) cm(-2), the design window of pillar width completely falls into the sub-micron range, indicating significant difficulties in fabrication. Vertical GaN SJ transistors with interface charges retain great advantages over conventional GaN power transistors, but have narrower design windows and require different design rules compared to ideal GaN SJ devices.

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